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IDT72403L35P Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72403L35P Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 9 page OCTOBER 2005 © 2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2747/10 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1 IDT72401 IDT72403 CMOSPARALLELFIFO 64 x 4 and 64 x 5 FEATURES: ••••• First-ln/First-Out Dual-Port memory ••••• 64 x 4 organization (IDT72401/72403) ••••• RAM-based FIFO with low falI-through time ••••• Low-power consumption — Active: 175mW (typ.) ••••• Maximum shift rate — 45MHz ••••• High data output drive capability ••••• Asynchronous and simultaneous read and write ••••• Fully expandable by bit width ••••• Fully expandable by word depth ••••• IDT72403 have Output Enable pin to enable output data ••••• High-speed data communications applications ••••• High-performance CMOS technology ••••• Available in CERDIP, plastic DIP and SOIC ••••• Military product compliant to MlL-STD-883, Class B ••••• Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function. ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available (plastic packages only) DESCRIPTION: The IDT72401 and IDT72403 are asynchronous high-performance First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also has an Output Enable ( OE) pin. The FlFOs accept 4-bit data at the data input (D0-D3). The stored data stack up on a first-in/first-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal canalsobeusedtocascademultipledevicestogether.TheOutputReady(OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The OR can also be used to cascade multiple devices together. WidthexpansionisaccomplishedbylogicallyANDingtheIRandORsignals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The IR pin of the receiving device is connected to the SO pin of the sending device and the OR pin of the sending device is connected to the Shift In (SI) pin of the receiving device. Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FlFOs ideal for high- speed communication and controller applications. Militarygradeproductismanufacturedincompliancewiththelatestrevision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM WRITE POINTER INPUT CONTROL LOGIC 2747 drw01 SI DATA IN MASTER RESET WRITE MULTIPLEXER MEMORY ARRAY READ POINTER READ MULTIPLEXER IR D0-3 MR OUTPUT ENABLE DATA IN MASTER RESET SO OR Q0-3 OE (IDT72403 only) |
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