OCTOBER 2005

© 2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-2747/10

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1

IDT72401

IDT72403

CMOSPARALLELFIFO

64 x 4 and 64 x 5

FEATURES:

— Active: 175mW (typ.)

5962-89523 is listed on this function.

°°°°°C to +85°°°°°C) is available

(plastic packages only)

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high-performance

First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also

has an Output Enable (

OE) pin. The FlFOs accept 4-bit data at the data input

A Shift Out (SO) signal causes the data at the next to last word to be shifted

to the output while all other data shifts down one location in the stack. The Input

Ready (IR) signal acts like a flag to indicate when the input is ready for new

data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal

canalsobeusedtocascademultipledevicestogether.TheOutputReady(OR)

signal is a flag to indicate that the output remains valid data (OR = HIGH) or

to indicate that the FIFO is empty (OR = LOW). The OR can also be used to

cascade multiple devices together.

WidthexpansionisaccomplishedbylogicallyANDingtheIRandORsignals

to form composite signals.

Depth expansion is accomplished by tying the data inputs of one device to

the data outputs of the previous device. The IR pin of the receiving device is

connected to the SO pin of the sending device and the OR pin of the sending

device is connected to the Shift In (SI) pin of the receiving device.

Reading and writing operations are completely asynchronous allowing the

FIFO to be used as a buffer between two digital machines of widely varying

operating frequencies. The 45MHz speed makes these FlFOs ideal for high-

speed communication and controller applications.

Militarygradeproductismanufacturedincompliancewiththelatestrevision

of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WRITE POINTER

INPUT

CONTROL

LOGIC

2747 drw01

SI

MASTER

RESET

WRITE MULTIPLEXER

MEMORY

ARRAY

READ POINTER

READ MULTIPLEXER

IR

MR

OUTPUT

ENABLE

MASTER

RESET

SO

OR

OE

(IDT72403 only)