MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

6

Figure 6. The Mechanism of Shifting Data Out of the FIFO

NOTES:

1. OR HIGH indicates that data is available and a SO pulse may be applied.

2. SO goes HIGH causing the next step.

3. OR goes LOW.

4. The read pointer is incremented.

5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.

6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.

7. SO pulses applied when OR is LOW will be ignored.

Figure 5. Output TIming

STABLE DATA

SO

SI

IR

INPUT DATA

(2)

(3)

(1)

(4)

(5)

2747 drw 08

NOTES:

1. FIFO is initially full.

2. SO pulse is applied.

3. SI is held HIGH.

4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

SO

OR

OUTPUT DATA

A- DATA

(2)

(3)

(5)

2747 drw 10

(6)

(4)

(1)

(7)

A or B

B- DATA

SO

OR

OUTPUT DATA

2747 drw 09

C-DATA

B-DATA

A-DATA

(2)

(1)

NOTES:

1. This data is loaded consecutively A, B, C.

2. Data is shifted out when SO makes a HIGH to LOW transition.