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IDT72T54252L5BBI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72T54252L5BBI Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 56 page  8 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO 32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2 MARCH 22, 2005 PAF0/1/2/3 Programmable HSTL-LVTTL This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin (Continued) Almost-Full Flags0-3 OUTPUT(1) during master reset. If Dual mode is selected PAF1 and PAF3 are not used and can be left floating. PD Power Down HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input INPUT level translators for all the data input pins, clocks and non-essential control pins are turned off. When PD is brought high, power-up sequence timing will have to be adhered to before the inputs will be recognized. It is essential that the user respect these conditions when powering down the part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks are free running. PD does not provide any power consumption savings when the inputs are configured for LVTTL. PFM Programmable CMOS(2) During master reset, a HIGH on PFM selects synchronous PAE/PAF flag timing, a Low during Flag Mode INPUT master reset selects asynchronous PAE/PAFflagtiming.ThispincontrolsallPAE/PAFflagoutputs. PRS0/1/2/3 PartialReset HSTL-LVTTL These are the partial reset inputs for each internal FIFO. The read, write, flag pointers, and output INPUT registers will all be set to zero when partial reset is activated. During partial reset, the existing mode (IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all retained. If Dual mode is selected, PRS1 and PRS3 are not used and should be tied to VCC. Q[39:0] Data Output Bus HSTL-LVTTL These are the Data Outputs for the device. Data is read from the part via these outputs using the OUTPUT(1) respective read port clocks and enables. In Quad mode, these outputs provide four separate busses from the four separate FIFO's. Q[9:0] is FIFO[0], Q[19:10] is FIFO[1], Q[29:20] is FIFO[2], Q[39:30] is FIFO[3]. In Dual mode these outputs provide two separate busses from the two separate FIFO's. Q[19:0] is FIFO[0] and Q[39:20] is FIFO[2]. RCLK0/1/2/3 Read Clock 0/1/2/3 HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the read port. If Dual mode INPUT is selected then RCLK1 and RCLK3 are not used and should be tied to GND. In SDR mode data willbeaccessedontherisingedgeofRCLKwhen RENandRCSareLOWattherisingedgeofRCLK. In DDR mode data will be accessed on both rising and falling edge of RCLK when REN is LOW. RCS0/1/2/3 Read Chip Select HSTL-LVTTL These are the read chip select inputs corresponding to each of the four FIFOs on the read port. This INPUT pin provides synchronous control of the read port and high impedance control of the output data bus. RCS is only sampled on the rising edge of RCLK. During master or partial reset this input is a don’t care, if OE is LOW the data inputs will be in Low-Impedance regardless of the state of RCS. If Dual mode is selected then RCS1 and RCS3 are not used and should be tied to VCC. REN0/1/2/3 Read Enable HSTL-LVTTL These are the read enable inputs corresponding to each of the four FIFOs on the read port. In SDR, INPUT when this signal (and RCS) are LOW data will be sent from the FIFO memory to the output bus on every rising edge of RCLK. In DDR mode, data will be accessed on both rising and falling edges of RCLK. Note in DDR mode the REN and RCS are only sampled on the rising edge of RCLK. New data will always begin from the rising edge not the falling edge of RCLK. If Dual mode is selected then REN1 and REN3 are not used and should be tied to VCC. RDDR Read Port DDR CMOS(2) Duringmasterreset,thispinselectstheoutputporttooperateinDDRorSDRformat.IfRDDRisHIGH, INPUT then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs. SCLK Serial Clock HSTL-LVTTL Serial clock for writing and reading the PAE and PAF offset registers. On the rising edge of each INPUT SCLK,when SWENislow,onebitofdataisshiftedintothePAEandPAFregisters.Ontherisingedge of each SCLK, when SREN is low, one bit of data is shifted out of the PAEand PAF offset registers. The reading of the PAEandPAFregistersisnon-destructive.IfprogrammingofthePAE/PAFoffset registers are done via the JTAG port, this input must be tied to VCC. SDO Serial Data LVTTL This output is used to read data from the programmable flag offset registers. It is used in conjunction OUTPUT(1) with the SREN and SCLK signals. SREN Serial Read Enable HSTL-LVTTL When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF INPUT offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin. Ifprogrammingofthe PAE/PAFoffsetregistersisdoneviatheJTAGport,thisinputmustbetiedHIGH. SWEN Serial Write Enable HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded INPUT into the PAE and PAF registers. If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied HIGH. Symbol Name I/O Type Description PIN DESCRIPTIONS (CONTINUED) |
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