IDT72T54262 datasheet(4/56 Pages) IDT

Part #	IDT72T54262

Description	2.5V QUAD/DUAL TeraSync??DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS

Download	56 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

Logo

4 / 56 page

4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

MARCH 22, 2005

DESCRIPTION

The IDT72T54242/72T54252/72T54262 Quad/Dual TeraSync FIFO

devices are ideal for many applications where data stream convergence and

parallel buffering of multiple data paths are required. These applications may

include communication systems such as data bandwidth aggregation, data

acquisition systems and medical equipment, etc. The Quad/Dual FIFO allows

theusertoselecteithertwoorfourindividualinternalFIFOsforoperation.Each

internal FIFO has its own discrete read and write clock, independent read and

write enables, and separate status flags. The density of each FIFO is fixed.

IfQuadmodeisselected,therewillbeatotalofeightclockdomains,fourread

and four write clocks. Data can be written into any of the four write ports totally

independent of any other port, and can be read out of any of the four read ports

corresponding to their respective write port. Each port has its own control

enables and status flags and is 10 bits wide. The device functions as four

separate 10-bit wide FIFOs.

If Dual mode is selected, there will be a total of four clock domains, two read

and two write clocks. Data can be written into any of the two write ports totally

independent of any other port, and can be read out of any of the two read ports

corresponding to their respective write port. Each port has its own control

enables and status flags. All input and output ports have bus-matching

capabilities of x10 or x20 bits wide.

As typical with most IDT FIFOs, two types of data transfer are available, IDT

Standard mode and First Word Fall Through (FWFT) mode. This affects the

deviceoperationandalsotheflagoutputs.Thedeviceprovideseightflagoutputs

perinputandoutputport.AdedicatedSerialClockisusedforprogrammingthe

flagoffsets.Thisclockisalsousedforreadingtheoffsetvalues. Theserialread

and write operations are performed via the SCLK, FWFT/SI,

SWEN, SREN,

and SDO pins. The flag offsets can also be programmed using the JTAG port.

If this option is selected, the SCLK,

SWEN,andSRENpinsmustbedisabled.

TheQuad/Dualdeviceoffersamaximumthroughputof2Gbpsperport,with

selectableSDRorDDRdatatransfermodesfortheinputsandoutputs.InSDR

mode, the input clock can operate up to 200MHz. Data will transition/latch on

therisingedgeoftheclock.InDDRmode,theinputclockcanoperateupto100

MHz,withdatatransitioning/latchedonbothrisingandfallingedgesoftheclock.

The advantage of DDR is that it can achieve the same throughput as SDR with

only half the number of bits, assuming the frequency is constant. For example,

a 4Gbps throughput in SDR is 100MHz x 40 bits. In DDR mode, it is 100MHz

x 20 bits, because two bits transition per clock cycle.

All Read ports provide the user with a dedicated Echo Read Enable,

EREN

and Echo Read Clock, ERCLK output. These outputs aid in high speed

applications where synchronization of the input clock and data of receiving

device is critical. Otherwise known as “Source Synchronous Clocking,” the

echo outputs provide tighter synchronization of the data transmitted from the

FIFO and the read clock interfacing the FIFO outputs.

A Master Reset input is provided and all setup and configuration pins are

latched with respect to a Master Reset pulse. For example, the mode of

operation,bus-matching,anddatarateareselectedatMasterReset. APartial

Reset is provided for each internal FIFO. When a Partial Reset is performed

on a FIFO the read and write pointers of that FIFO are reset to the first memory

location. The flag offset values, timing modes, and initial configurations are

retained.

The Quad/Dual device has the capability of operating its I/O at either 2.5V

LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input

is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the

IOSELpin. Thecoresupplyvoltageofthedevice,VCCisalways2.5V,however

theoutputpinshaveaseparatesupply,VDDQwhichcanbe2.5V,1.8V,or1.5V.

Theinputsofthisdeviceare3.3VtolerantwhenVDDQissetto2.5V. Thedevice

also offers significant power savings, most notably achieved by the presence

of a Power Down input,

PD.

A JTAG test port is provided. The Quad/Dual device has a fully functional

BoundaryScanfeature,compliantwithIEEE1149.1StandardTestAccessPort

and Boundary Scan Architecture.

Similar Part No. - IDT72T54262

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72T51233	532Kb / 55P	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
	IDT72T51233L5BB	532Kb / 55P	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
	IDT72T51233L5BBI	532Kb / 55P	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
	IDT72T51233L6BB	532Kb / 55P	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
	IDT72T51233L6BBI	532Kb / 55P	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits

More results

Similar Description - IDT72T54262

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72T4088	497Kb / 52P	2.5 VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 40-BIT CONFIGURATION
	IDT72T3645	472Kb / 57P	2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS
	IDT72T7285	465Kb / 53P	2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS
	IDT72T2098	481Kb / 51P	2.5 VOLT HIGH-SPEED TeraSync??DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
	IDT72T36135M	479Kb / 48P	2.5V 18M-BIT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS 524,288 x 36
Exar Corporation	XR16C854	476Kb / 51P	QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
Integrated Device Techn...	IDT7280	149Kb / 12P	CMOS DUAL ASYNCHRONOUS FIFO
	IDT72T18125	540Kb / 55P	2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
	IDT72T1845	510Kb / 55P	2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
Texas Instruments	TL16C754	488Kb / 39P	[Old version datasheet] QUAD UART WITH 64-BYTE FIFO

More results

IDT72T54262 Datasheet(PDF) 4 Page - Integrated Device Technology

IDT72T54262 Datasheet(HTML) 4 Page - Integrated Device Technology

Similar Part No. - IDT72T54262

Similar Description - IDT72T54262

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL