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IDT72T54242 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72T54242 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 56 page 7 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO 32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2 MARCH 22, 2005 Symbol Name I/O Type Description D[39:0] Data Input Bus HSTL-LVTTL Thesearethedatainputsforthedevice.Dataiswrittenintothepartviatheseinputsusingtherespective INPUT write port clocks and enables. In Quad mode, these inputs provide four separate busses to the four separate FIFOs. D[9:0] is FIFO[0], D[19:10] is FIFO[1], D[29:20] is FIFO[2], D[39:30] is FIFO[3]. InDualmode,theseinputsprovidetwoseparatebussestothetwoseparateFIFOs.D[19:0]isFIFO[0], D[39:20] is FIFO[2]. Any unused inputs should be tied to GND. EF0/1/2/3, Empty Flag 0/1/2/3 HSTL-LVTTL ThesearetheEmptyFlags(IDTStandardmode)orOutputReadyFlag(FWFTmode)corresponding OR0/1/2/3 or Output Ready OUTPUT(1) to each of the four FIFOs on the read port. If Dual mode is selected EF1/OR1 and EF3/OR3 are Flags 0/1/2/3 not used and can be left floating. ERCLK0/1/2/3 Echo Read Clock HSTL-LVTTL These are the echo clock outputs corresponding to each of the four FIFOs on the read port. The 0/1/2/3 OUTPUT(1) echo read clock is guaranteed to transition after the slowest output data switching. If Dual mode is selected ERCLK1 and ERCLK3 are not used and can be left floating EREN0/1/2/3 Echo Read Enable HSTL-LVTTL These are the echo read enable outputs corresponding to each of the four FIFOs on the read port. 0/1/2/3 OUTPUT(1) The echo read enable is synchronous to the RCLK input and is active when a read operation has occurred and a new word has been placed onto the data output bus. If Dual mode is selected EREN1 and EREN3 are not used and can be left floating. FF0/1/2/3, Full Flags 0/1/2/3 or HSTL-LVTTL These are the Full Flags (IDT Standard mode) and Input Ready Flags (FWFT mode) corresponding IR0/1/2/3 Input Ready Flags OUTPUT(1) to each of the four FIFOs on the read port. If Dual mode is selected FF1/IR1 and FF3/IR3 are not 0/1/2/3 used and can be left floating. FSEL Flag Select HSTL-LVTTL Flagselectdefaultoffsetpins.Duringmasterreset,theFSELpinsareusedtoselectoneoffourdefault [1:0] INPUT PAEandPAFoffsets.BoththePAEandthePAFoffsetsareprogrammedtothesamevalue.Values are: 00 = 7; 01 = 63; 10 = 127; 11 = 1023. The offset value selected is supplied to all internal FIFOs. FWFT/SI First Word Fall HSTL-LVTTL DuringMasterReset,FWFT=1selectsFirstWordFallThroughmode,FWFT=0selectsIDTStandard Through/ Serial INPUT mode.AfterMasterResetthispinisusedfortheSerialDatainputfortheprogrammingofthe PAEand Input PAFflag'soffsetregisters. IOSEL I/OSelect CMOS(2) This input determines whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL INPUT pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be set to HSTL. If IOSEL is LOW then LVTTL is selected. This signal must be tied to either VCC or GND for proper operation. IW InputWidth CMOS(2) If Dual mode is selected , this pin is used during master reset to select the input word width bus size INPUT for the device. 0 = x10; 1 = x20. If Quad mode is selected the input word width will be x10 regardless of IW. IW must be tied to VCC or GND and cannot be left floating. MD Mode CMOS(2) This mode selection pin is used during master reset to select either Quad or Dual mode operation. INPUT A HIGH on this pin selects Quad mode, a LOW selects Dual mode. MRS Master Reset HSTL-LVTTL This input provides a full device reset. All set-up pins are latched based on a master reset operation. INPUT Read and write pointers will be reset to the first location memory. All flag offsets are cleared and reset to default values determined by FSEL[1:0]. OE0/1/2/3 OutputEnable HSTL-LVTTL ThesearetheoutputenablescorrespondingtoeachindividualFIFOonthereadport.Alldataoutputs 0/1/2/3 INPUT will be placed into High Impedance if this pin is High. These inputs are asynchronous. If Dual mode is selected OE1 and OE3 are not used and should be tied to VCC. OW OutputWidth CMOS(2) If Dual mode is selected, this pin is used during master reset to select the output word width bus size INPUT for the device. 0 = x10; 1 = x20. If Quad mode is selected the output word width will be x10 regardless of OW. OW must be tied to VCC or GND and cannot be left floating. PAE0/1/2/3 Programmable HSTL-LVTTL These are the programmable almost empty flags that can be used as an early indicator for the empty Almost-Empty OUTPUT(1) boundary of each FIFO. The PAE flags can be set to one of four default offsets determined by the Flags 0/1/2/3 state of FSEL0 and FSEL1 during master reset. The PAEoffset value can also be written and read from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN,SREN). This flag can operate in synchronous or asynchronous mode depending on the sate of the PFM pin during master reset. If Dual mode is selected PAE1 and PAE3 are not used and can be left floating. PAF0/1/2/3 Programmable HSTL-LVTTL These are the programmable almost full flags that can be used as an early indicator for the full Almost-Full Flags OUTPUT(1) boundary of each FIFO. The PAF flags can be set to one of four default offsets determined by the 0/1/2/3 state of FSEL0 and FSEL1 during master reset. The PAF offset value can also be written and read from serially by either the JTAG port or the serial programming pins (SCLK, SI, SDO, SWEN,SREN). PIN DESCRIPTIONS |
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