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P4C164-10PMBLF Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C164-10PMBLF Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 16 page 1 Document # SRAM115 REV F Revised June 2007 FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 8/10/12/15/20/25/35/70/100 ns (Commercial) – 10/12/15/20/25/35/70/100 ns(Industrial) – 12/15/20/25/35/45/70/100 ns (Military) Low Power Operation Output Enable and Dual Chip Enable Control Functions Single 5V±10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C164L Military) Common Data I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil Plastic DIP, SOJ – 28-Pin 600 mil Plastic DIP (70 & 100ns) – 28-Pin 300 mil SOP (70 & 100ns) – 28-Pin 300 mil Ceramic DIP – 28-Pin 600 mil Ceramic DIP – 28-Pin 350 x 550 mil LCC – 32-Pin 450 x 550 mil LCC – 28-Pin CERPACK P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS DESCRIPTION The P4C164 is a 65,536-bit ultra high-speed static RAM organized as 8K x 8. The CMOS memory requires no clocks or refreshing and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS 1519B DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), CERPACK (F4), SOP(S6) SEE PAGE 7 FOR LCC PIN CONFIGURATIONS Access times as fast as 8 nanoseconds are available, permitting greatly enhanced system operating speeds. The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28- pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK. The 70ns and 100ns P4C164s are available in the 600 mil plastic DIP. |
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