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CY7C1356C-166AXI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1356C-166AXI
Description  9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1356C-166AXI Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 9 of 28
NOP/WRITE ABORT (Begin Burst)
None
L
L
L
L
H
X
L
L-H
Tri-State
WRITE ABORT (Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Tri-State
IGNORE CLOCK EDGE (Stall)
Current
X
L
X
X
X
X
H
L-H
-
SLEEP MODE
None
X
H
X
X
X
X
X
X
Tri-State
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1354C)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
HHH
L
Write Byte b – (DQb and DQPb)L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
LHLH
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1356C)
WE
BWb
BWa
Read
Hx
x
Write – No Bytes Written
L
H
H
Write Byte a
− (DQ
a and DQPa)
LHL
Write Byte b – (DQb and DQPb)
LL
H
Write Both Bytes
L
L
L
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
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