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IDT82V2048LBB Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT82V2048LBB Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 48 page  5 IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END INDUSTRIAL TEMPERATURE RANGES Transmit and Receive Digital Data Interface TDP0 TDP1 TDP2 TDP3 TDP4 TDP5 TDP6 TDP7 TDN0 TDN1 TDN2 TDN3 TDN4 TDN5 TDN6 TDN7 I 37 30 80 73 108 101 8 1 38 31 79 72 109 102 7 144 N2 L2 L13 N13 B13 D13 D2 B2 N3 L3 L12 N12 B12 D12 D3 B3 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7 The NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are active high and are sampled on the falling edges of TCLKn. TCLK0 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 I 36 29 81 74 107 100 9 2 N1 L1 L14 N14 B14 D14 D1 B1 TCLKn: Transmit Clock for Channel 0~7 The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The transmit data at TDPn or TDNn is sampled into the device on the falling edges of TCLKn. Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as Table-2 System Interface Configuration. RDP0 RDP1 RDP2 RDP3 RDP4 RDP5 RDP6 RDP7 RDN0 RDN1 RDN2 RDN3 RDN4 RDN5 RDN6 RDN7 O High Imped- ance 40 33 77 70 111 104 5 142 41 34 76 69 112 105 4 141 P2 M2 M13 P13 A13 C13 C2 A2 P3 M3 M12 P12 A12 C12 C3 A3 RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7 These pins output the raw RZ sliced data. The active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is low, RDPn/RDNn is active low. When pin CLKE is high, RPDn/RDNn is active high. RDPn/RDNn will remain active during LOS. RDPn/RDNn is set into high impedance when the correspond- ing receiver is powered down. RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 O High Imped- ance 39 32 78 71 110 103 6 143 P1 M1 M14 P14 A14 C14 C1 A1 RCn: Receive Pulse for Channel 0~7 RCn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock is recovered from the signal on RCn. If receiver n is powered down, the corresponding RCn will be in high impedance. Table-1 Pin Description (Continued) Name Type Pin No. Description TQFP144 PBGA160 TDPn TDNn Output Pulse 0 0 Space 0 1 Negative Pulse 1 0 Positive Pulse 1 1 Space |
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