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IDT79RC64V474-180DP Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT79RC64V474-180DP Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 25 page  2 of 25 April 10, 2001 RC64474™ RC64475™ Device Overview1 Extending Integrated Device Technology’s (IDT) RISCore4000 based choices (see Table 1), the RC64474 and RC64475 are high perfor- mance 64-bit microprocessors targeted towards applications that require high bandwidth, real-time response and rapid data processing and are ideal for products ranging from internetworking equipment (switches, routers) to multimedia systems such as web browsers, set-top boxes, video games, and Windows®CE based products. These processors are rated at 330 Dhrystone MIPS and 125 Million floating point operations per second, at 250 MHz. The internal cache bandwidth for these devices is over 3GB/second. The 64-bit external bus bandwidth is at more than 1000MB/s, and the 32-bit external bus bandwidth is at 500MB/s. The RC64474 is packaged in a 128-pin QFP footprint package and uses a 32-bit external bus, offering the ideal combination of 64-bit processing power and 32-bit low-cost memory systems. The RC64475 is packaged in a 208-pin QFP footprint package and uses the full 64-bit external bus. The RC64475 is ideal for applications requiring 64-bit performance and 64-bit external bandwidth. IDT’s RISCore4000 is a 250MHz 64-bit execution core that uses a 5-stage pipeline, eliminating the “issue restrictions” associated with other more complex pipelines. The RISCore4000 implements the MIPS-III Instruction Set Architecture (ISA) and is upwardly compatible with applications that run on earlier generation parts. Implementation of the MIPS-III architecture results in 64-bit opera- tions, improved performance for commonly used code sequences in 1. Detailed system operation information is provided in the RC64474/RC64475 user’s manual. operating system kernels, and faster execution of floating-point intensive applications. The RISCore4000 integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The ALU consists of the integer adder and logic unit. The adder performs address calculations in addition to arithmetic operations, and the logic unit performs all of the processor’s logical and shift operations. Each unit is highly optimized and can perform an operation in a single pipeline cycle. Both 32- and 64-bit data operations are performed by the RISCore4000, utilizing 32 general purpose 64-bit registers (GPR) that are used for integer operations and address calculation. A complete on-chip floating-point co-processor (CP1), which includes a floating-point register file and execution units, forms a “seamless” interface, decoding and executing instructions in parallel with the integer unit. CP1’s floating-point execution units support both single and double precision arithmetic—as specified in the IEEE Standard 754— and are separated into a multiply unit and a combined add/convert/ divide/square root unit. Overlap of multiplies and add/subtract is supported, and the multiplier is partially pipelined, allowing the initiation of a new multiply instruction every fourth pipeline cycle. The floating-point register file is made up of thirty-two 64-bit regis- ters. The floating-point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle. The RISCore4000’s system control coprocessor (CP0) registers are also incorporated on-chip and provide the path through which the virtual memory system’s page mapping is examined and changed, exceptions are handled, and any operating mode selections are controlled. RISCore4000/RISCore5000 Family of Socket Compatible Processors Table 1 RISCore4000/RISCore5000 Processor Family 32-bit Processors 64-bit Processors RC4640 RC64474 RC64574 RC4650 RC64475 RC64575 CPU 64-bit RISCore4000 w/ DSP extensions 64-bit RISCore4000 64-bit RISCore5000 w/ DSP extensions 64-bit RISCore4000 w/ DSP extensions 64-bit RISCore4000 64-bit RISCore5000 w/ DSP extensions Performance >350MIPS >330MIPS >440MIPS >350MIPS >330MIPS >440MIPS FPA 89 mflops, single pre- cision only 125 mflops, single and double precision 666 mflops, single and double precision 89 mflops, single pre- cision only 125 mflops, single and double precision 666 mflops, single and double precision Caches 8kB/8kB, 2-way, lock- able by set 16kB/16kB, 2-way, lockable by set 32kB/32kB, 2-way, lockable by line 8kB/8kB, 2-way, lock- able by set 16kB/16kB, 2-way, lockable by set 32kB/32kB, 2-way, lockable by line External Bus 32-bit 32-bit, Superset pin compatible w/RC4640 32-bit, Superset pin compatible w/RC4640, RC64474 32- or 64-bit 32-or 64-bit, Super- set pin compatible w/ RC4650 32-or 64-bit, Super- set pin compatible w/ RC4650, RC64475 Voltage 3.3V 3.3V 2.5V 3.3V 3.3V 2.5V Frequencies 100-267 MHz 180-250 MHz 200-333 MHz 100-267 MHz 180-250 MHz 200-333 MHz Packages 128 PQFP 128 QFP 128 QFP 208 QFP 208 QFP 208 QFP MMU Base-Bounds 96 page TLB 96 page TLB Base-Bounds 96 page TLB 96 page TLB Key Features Cache locking, on- chip MAC, 32-bit external bus Cache locking, JTAG, syncDRAM mode, 32- bit external bus Cache locking, JTAG, syncDRAM mode, 32- bit external bus Cache locking, on- chip MAC, 32-bit & 64 bit bus option Cache locking, JTAG, syncDRAM mode, 32- 64- bit bus option Cache locking, JTAG, syncDRAM mode, 32- 64- bit bus option |
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