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IDT79RC64T575-200DZ Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT79RC64T575-200DZ Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 28 page 8 of 28 December 14, 2001 79RC64574™ 79RC64575™ Interrupt Interface Int*(5:0) I Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. NMI* I Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register. Initialization Interface VCCOkI VCC is OK When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization sequence. ColdReset* I Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchro- nously with SysClock. Reset* I Reset This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. ModeClock O Boot-mode clock Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six. ModeIn I Boot-mode data in Serial boot-mode data input. JTAG Interface TDI I JTAG Data In On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register, depending on the TAP controller state. An external pull-up resistor is required. TDO O JTAG Data Out On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When no data is shifted out, the TDO is tri-stated (high impedance). TCK I JTAG Clock Input An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the sys- tem and processor clock with nominal 40-60% duty cycle. TMS I JTAG Command Select The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising edge of TCK. An external pull-up resistor is required. TRST* I JTAG Reset The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the pro- cessor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this active low pin. When asserted low, this pin will also tristate the TDO pin. An external pull-down resistor is required. JTAG32* I JTAG 32-bit scan This pin is used to control length of the scan chain for SysAD (32-bit or 64-bit) for the JTAG mode. When set to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in pull-down device to guarantee 32-bit scan, if it is left un connected. JR_Vcc I JTAG VCC This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset. Pin Name Type Description Table 5 Pin Descriptions (Page 2 of 2) |
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