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CY7C1351G-133AXC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7C1351G-133AXC
Description  4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1351G-133AXC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7C1351G
Document #: 38-05513 Rev. *D
Page 4 of 14
Functional Overview
The CY7C1351G is a synchronous flow-through burst SRAM
designed
specifically
to
eliminate
wait
states
during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within
6.5 ns (133-MHz device) provided OE is active LOW. After the
first clock of the read access, the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW
in order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ZZ
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.
DQs
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the read cycle. The direction of the pins is controlled
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQs and DQP[A:D] are placed in a tri-state condition. The outputs are automatically
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
DQP[A:D]
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply Power supply for the I/O circuitry.
VSS
Ground
Ground for the device.
NC
No Connects. Not Internally connected to the die.
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
Pin Definitions (continued)
Name
I/O
Description
[+] Feedback
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