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IDT72T36135M Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72T36135M Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 48 page  COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36 3 MAY 29, 2006 DESCRIPTION: The IDT72T36135M is an exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memoriy with clocked read and write controls and a wide extended x36 bus to allow ample data flow. These FIFOs offer several key user benefits: • High density offering of 18 Mbit • 200MHz R/W Clocks supporting 7.2Gbps of data throughput • User selectable MARK location for retransmit • User selectable I/O structure for HSTL or LVTTL • Asynchronous/Synchronous translation on the read or write ports • Thefirstworddatalatencyperiod,fromthetimethefirstwordiswritten to an empty FIFO to the time it can be read, is fixed and short. TeraSync FIFOs are particularly appropriate for network, video, telecom- munications, data communications and other applications that need to buffer large amounts of data at very high performance. Theinput portcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the input port is controlledbyaWriteClock(WCLK)inputandaWriteEnable( WEN)input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The input port can be selected for either 2.5V LVTTL or HSTL operation, thisoperationisselectedbythestateoftheWHSTLinputduringamasterreset. A Write Chip Select input ( WCS) is provided for use when the write port is in both LVTTL and HSTL modes. During operation the WCS input can be used to disable write port inputs (data only). TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable ( REN)input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport the FIFO must be configured for Standard IDT mode, also the RCSshouldbe tiedLOWandthe OEinputusedtoprovidethree-statecontroloftheoutputs,Qn. The output port can be selected for either 2.5V LVTTL or HSTL operation, thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset. AnOutputEnable( OE)inputisprovidedforthree-statecontroloftheoutputs. AReadChipSelect( RCS)inputisalsoprovided,theRCSinputissynchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronousoperationoftheoutputport, RCSshouldbeenabled,heldLOW. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating RENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A RENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. The 18M-bit TeraSync FIFO has 8 flag pins, EF/OR[1:2] (Empty Flag or Output Ready), FF/IR[1:2] (Full Flag or Input Ready), PAE[1:2] (Program- mableAlmost-Emptyflag)and PAF[1:2](ProgrammableAlmost-Fullflag). The EF[1:2]andFF[1:2] functionsareselectedinIDTStandardmode. TheIR[1:2] and OR[1:2]functionsareselectedinFWFTmode.PAE[1:2]andPAF[1:2]are always available for use, irrespective of timing mode. Each flag has a double because the 18M FIFO was designed as a Multi-chip Module, so each set of flagssupportsitsrespectiveinternal9MFIFO. Someextraexternalgatinglogic will have to be used to accurately read each flag output. This will be covered in the flagging section of the datasheet. PAE[1:2]andPAF[1:2]canbeprogrammedindependentlytoswitchatany pointinmemory. Programmableoffsetsdeterminetheflagswitchingthreshold andcanbeloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettings are also provided, so that PAE[1:2]canbesettoswitchatapredefinednumber of locations from the empty boundary and the PAF[1:2] thresholdcanalsobe setatsimilarpredefinedvaluesfromthefullboundary. Thedefaultoffsetvalues are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WENtogetherwith LD oneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serial or parallel offset loading has been selected. During Master Reset ( MRS)thefollowingeventsoccur: thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmode of the PAE[1:2](Programmable Almost-Emptyflag)and PAF[1:2](ProgrammableAlmost-Fullflag)outputs.The timing modes can be set to be either asynchronous or synchronous for the PAE[1:2] and PAF[1:2] flags. If asynchronous PAE/PAF[1:2]configuration is selected, the PAE[1:2] is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE[1:2] is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF[1:2] is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF[1:2]isreset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF[1:2] configuration is selected , the PAE[1:2] is assertedandupdatedontherisingedgeofRCLKonlyandnotWCLK.Similarly, PAF[1:2] is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during MasterReset by the state of the Programmable Flag Mode (PFM) pin. ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol inputs, MARK and , RT(Retransmit).IftheMARKinputisenabledwithrespect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RTgoesLOW,willresetthereadpointerto this‘marked’location. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol |
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