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IDT74FCT543CTSO Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT74FCT543CTSO Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 7 page INDUSTRIALTEMPERATURERANGE 2 IDT74FCT543AT/CT/DT FASTCMOSOCTALLATCHEDTRANSCEIVER PIN CONFIGURATION Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 ° C IOUT DC Output Current –60 to +120 mA ABSOLUTE MAXIMUM RATINGS(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. SOIC/ QSOP TOP VIEW 2 3 1 20 19 18 15 16 9 10 A6 A7 B6 B7 23 22 24 21 17 5 6 7 4 8 A1 OEBA A0 VCC A2 A5 A3 A4 CEBA B2 B0 B1 B3 B4 B5 LEBA 13 14 11 12 CEAB GND LEAB OEAB PIN DESCRIPTION Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A0–A7 A-to-B Data Inputs or B-to-A 3-State Outputs B0–B7 B-to-A Data Inputs or A-to-B 3-State Outputs |
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