PRELIMINARY
CY7C1310CV18
CY7C1910CV18
CY7C1312CV18
CY7C1314CV18
Document #: 001-07164 Rev. *B
Page 7 of 26
Functional Overview
The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and
CY7C1314CV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1310CV18, two 9-bit data transfers in the case of
CY7C1910CV18,two 18-bit data transfers in the case of
CY7C1312CV18 and two 36-bit data transfers in the case of
CY7C1314CV18, in one clock cycle.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device will behave in QDR-I mode
with a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. For normal operation, this pin can be connected to a pull-up through
a 10-Kohm or less pull-up resistor. The device will behave in QDR-I mode when the DLL
is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
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