CY7C1345G
Document Number: 38-05517 Rev. *E
Page 7 of 20
Burst Sequences
The CY7C1345G provides an on-chip two-bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0] and
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Table 1. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Table 2. Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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