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P4C164-12PMLF Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation |
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P4C164-12PMLF Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation |
4 / 16 page P4C164 Page 4 of 16 Document # SRAM115 REV F AC ELECTRICAL CHARACTERISTICS—READ CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Notes: 5. WE is HIGH for READ cycle. 6. CE 1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE 1 transition LOW and CE 2 transition HIGH. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. TIMING WAVEFORM OF READ CYCLE NO. 1 ( OE OE OE OE OE CONTROLLED)(5) Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max tRC Read Cycle Time 8 1012152025 35 4570 100 ns tAA Address Access Time 8 10 12 152025354570 100 ns tAC Chip Enable Access Time 8 10 12 152025354570 100 ns tOH Output Hold from Address Change 333333333 3 ns tLZ Chip Enable to Output in Low Z 222222222 2 ns tHZ Chip Disable to Output in High Z 5678 8 10 15 20 35 45 ns tOE Output Enable Low to Data Valid 5679 10 13 18 20 35 45 ns tOLZ Output Enable Low to Low Z 222222222 2 ns tOHZ Output Enable High to High Z 5679 9 12 15 20 35 45 ns tPU Chip Enable to Power Up Time 000000000 0 ns tPD Chip Disable to Power Down Time 8 10 12 15202020253545 ns Symbol Parameter -8 -10 -12 -15 -20 -25 Unit -35 -45 -70 -100 |
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