CY7C1346H
Document #: 38-05672 Rev. *B
Page 3 of 16
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
feed the 2-bit counter.
BWA,BWB
BWC,BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a Read cycle when emerging from a
deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1
is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQA, DQB
DQC, DQD,
DQPA,
DQPB
DQPC,DQP
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed
in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
