CY7C1345G
Document Number: 38-05517 Rev. *E
Page 10 of 20
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state.............................................–0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001V
Latch up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V
−5%/+10%
2.5V –5%
to VDD
Industrial
–40°C to +85°C
Electrical Characteristics
Over the Operating Range [7, 8]
Parameter
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
IO Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
for 3.3V IO, IOH = –4.0 mA
2.4
V
for 2.5V IO, IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
for 3.3V, IO, IOL= 8.0 mA
0.4
V
for 2.5V IO, IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage
for 3.3V IO
2.0
VDD + 0.3V
V
for 2.5V IO
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[7]
for 3.3V IO
–0.3
0.8
V
for 2.5V IO
–0.3
0.7
V
IX
Input Leakage Current except
ZZ and MODE
GND
≤ VI ≤ VDDQ
−55
µA
Input Current of MODE
Input = VSS
–30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
–5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current
GND
≤ VI ≤ VDDQ, Output Disabled
–5
5
µA
IDD
VDD Operating Supply Current VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5 ns cycle, 133 MHz
225
mA
10 ns cycle, 100 MHz
205
mA
ISB1
Automatic CE Power down
Current—TTL Inputs
Max VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
7.5 ns cycle, 133 MHz
90
mA
10 ns cycle, 100 MHz
80
mA
ISB2
Automatic CE Power down
Current—CMOS Inputs
Max VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
40
mA
ISB3
Automatic CE Power down
Current—CMOS Inputs
Max VDD, Device Deselected,
VIN ≥ VDDQ – 0.3V or VIN ≤
0.3V, f = fMAX, inputs switching
7.5 ns cycle, 133 MHz
75
mA
10 ns cycle, 100 MHz
65
mA
ISB4
Automatic CE Power down
Current—TTL Inputs
Max VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
45
mA
Notes
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
8. TPower up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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