CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *E
Page 8 of 28
Functional Overview
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are synchronous pipelined Burst SRAMs
equipped with both a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
The QDR-II completely eliminates the need to “turn-around” the
data bus by having separate read and write ports. This avoids
any possible data contention, and thereby simpliflies system
design. Each access consists of two 8-bit data transfers in the
case of CY7C1310BV18, two 9-bit data transfers in the case of
CY7C1910BV18, two 18-bit data transfers in the case of
CY7C1312BV18, and two 36-bit data transfers in the case of
CY7C1314BV18, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are refer-
enced from the rising edge of the input clocks (K and K) and all
output timings are referenced to the rising edge of output clocks
(C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1312BV18 is described in the following sections. The
same
basic
descriptions
apply
to
CY7C1310BV18
CY7C1910BV18 and CY7C1314BV18.
Read Operations
The CY7C1312BV18 is organized internally as 2 arrays of 512K
x 18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
address is latched on the rising edge of the K Clock. The address
presented to address inputs is stored in the read address
register. Following the next K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
C as the output timing reference. On the subsequent rising edge
of C, the next 18-bit data word is driven onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the output
clock (C and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the Output Clocks (C/C). This
enables a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K clock
rise, the data presented to D[17:0] is latched and stored into the
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the Negative
Input Clock (K), the address is latched and the information
presented to D[17:0] is stored into the Write Data register provided
BWS[1:0] are both asserted active. The 36-bits of data is then
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after the pending
Write operations are completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1312BV18. A
Write operation is initiated as described in the Write Operations
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each 18-bit data word.
You can latch and write the data presented into the device by
asserting the appropriate Byte Write Select input during the data
portion of a Write. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1312BV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1312BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user can
Read or Write to any location, regardless of the transaction on
the other port. Also, reads and writes can be started in the same
clock cycle. If the ports access the same location at the same
time, the SRAM delivers the most recent information associated
with the specified address location. This includes forwarding
data from a Write cycle that was initiated on the previous K clock
rise.
Depth Expansion
The CY7C1312BV18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω, with VDDQ =1.5V.The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high speed systems. Two echo clocks are generated by the
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