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IDTIDT71P71804167BQ Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDTIDT71P71804167BQ Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 23 page  6.42 11 IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V) NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min)) 3. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min)) 4. This conditon is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at leaset the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC) VIL VDD VDD +0.25 VDD +0.5 20% tKHKH (MIN) 6112 drw 21 VSS VIH VSS-0.25V VSS-0.5V 20% tKHKH (MIN) 6112 drw 22 Overshoot Timing Undershoot Timing PARAMETER SYMBOL MIN MAX UNIT NOTES Input High Voltage, DC VIH (DC)VREF +0.1 VDDQ +0.3 V 1,2 Input Low Voltage, DC VIL (DC) -0.3 VREF -0.1 V 1,3 Input High Voltage, AC VIH (AC) VREF +0.2 - V 4,5 Input Low Voltage, AC VIL (AC) -VREF -0.2 V 4,5 6112 tbl 10d |
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