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CY7C1312BV18-167BZC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1312BV18-167BZC
Description  18-Mbit QDR??II SRAM 2 Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1312BV18-167BZC Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit QDR™-II SRAM 2 Word
Burst Architecture
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05619 Rev. *E
Revised July 15, 2007
Features
Separate Independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
2 Word Burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in x 8, x 9, x 18, and x 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
Available in 165 ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non-Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Functional Description
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array. The
read port has dedicated Data Outputs to support read operations
and the Write Port has dedicated Data Inputs to support write
operations. QDR-II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR-II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are equipped with Double Data Rate (DDR) interfaces.
Each address location is associated with two 8-bit words
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Since data is transferred
into and out of the device on every rising edge of both input
clocks (K and K and C and C), maximize the memory bandwidth
while
simplifying
system
design
by
eliminating
bus
“turn-arounds.”
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
600
550
500
mA


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