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IDT70121L55JG Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70121L55JG Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 15 page 7 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges APRIL 05, 2006 Timing Waveform of Read Cycle No. 1, Either Side(1,2,4) NOTES: 1. Timing depends on which signal is aserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/ W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW. Timing Waveform of Read Cycle No. 2, Either Side(5) ADDRESS DATAOUT tRC tOH PREVIOUS DATA VALID tAA tOH DATA VALID 2654 drw 05 tBDD (3,4) BUSYOUT CE tACE tHZ tLZ tPD VALID DATA tPU 50% OE DATAOUT CURRENT ICC ISS 50% 2654 drw 06 (4) (1) (1) (2) (2) (4) tLZ tHZ tAOE |
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