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PCA9534APWG4 Datasheet(PDF) 8 Page - Texas Instruments |
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PCA9534APWG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 35 page www.ti.com Interrupt Output (INT) Bus Transactions Writes SCL Start Condition Data 1 Valid SDA Write to Port Data Out From Port R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8 7 6 5 4 3 2 Data 1 1 A2 0 1 S 1 1 A1 A0 0 A 0 0 0 0 0 0 0 A A P tpv Data to Port Command Byte Slave Address Data 1/0 A2 0 1 S 1 1 A1 A0 0 A 1 0 0 0 0 0 0 A A P SCL SDA Data to Register Start Condition R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8 7 6 5 4 3 2 Data to Register Command Byte Slave Address PCA9534A REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS SCPS141B – SEPTEMBER 2006 – REVISED MARCH 2007 An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to VCC. Data is exchanged between the master and PCA9534A through write and read commands. Data is transmitted to the PCA9534A by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on the number of data bytes sent in one write transmission. Figure 6. Write to Output Port Register <br/> Figure 7. Write to Configuration or Polarity Inversion Registers 8 Submit Documentation Feedback |
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