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P4C1298-15CM Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C1298-15CM Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 11 page P4C1298/L Page 6 of 11 Document # SRAM135 REV OR 12. Write Cycle Time is measured from the last valid address to the first transition address. 13. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. Notes: 9. CE and WE must be LOW for WRITE cycle. 10. OE is LOW for this WRITE cycle. 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( WE WE WE WE WE CONTROLLED) (9) AC CHARACTERISTICS - WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Min Max MinMax MinMax MinMax MinMax tWC Write Cycle Time 15 20 25 35 45 tCW Chip Enable Time to End of Write 10 15 20 25 30 tAW Address Valid to End of Write 10 15 20 25 30 tAS Address Set-up Time 000 00 tWP Write Pulse Width 10 15 20 25 30 tAH Address Hold Time from End of Write 0 0 0 0 0 tDW Data Valid to End of Write 9 10 15 20 20 tDH Data Hold Time 000 00 tWZ Write Enable to Output in High Z 7 10 15 20 20 tOW Output Active from End of Write 0 0 0 0 0 Sym Parameter -45 -15 -20 -25 -35 |
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