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CY7C1257V18-300BZXI Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1257V18-300BZXI
Description  36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1257V18-300BZXI Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Document Number: 001-06348 Rev. *C
Page 10 of 27
Write Cycle Descriptions
The write cycle descriptions table for CY7C1246V18 and CY7C1248V18 follows.[2, 8]
BWS0/
NWS0
BWS1/
NWS1
K
K
Comments
L
L
L–H
During the data portion of a write sequence
:
CY7C1246V18
− both nibbles (D[7:0]) are written into the device,
CY7C1248V18
− both bytes (D[17:0]) are written into the device.
L
L
L-H During the data portion of a write sequence
:
CY7C1246V18
− both nibbles (D[7:0]) are written into the device,
CY7C1248V18
− both bytes (D[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
:
CY7C1246V18
− only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1248V18
− only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
:
CY7C1246V18
− only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1248V18
− only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
:
CY7C1246V18
− only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1248V18
− only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
:
CY7C1246V18
− only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1248V18
− only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
L–H
No data is written into the devices during this portion of a write operation.
H
H
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle descriptions table for CY7C1257V18 follows.[2, 8]
BWS0
KK
Comments
L
L-H
During the data portion of a write sequence
, the single byte (D[8:0]) is written into the device.
L
L-H
During the data portion of a write sequence
, the single byte (D[8:0]) is written into the device.
H
L-H
No data is written into the device during this portion of a write operation.
H
L-H
No data is written into the device during this portion of a write operation.
Note
8. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are met.
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