CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *E
Page 7 of 28
K
Input-Clock
Negative Input Clock Input. K captures synchronous inputs presented to the device and drives out
data through Q[x:0] when in single clock mode.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K.
The timings for the echo clocks are shown in the “Switching Characteristics” on page 22.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K.
The timings for the echo clocks are shown in the “Switching Characteristics” on page 22.
ZQ
Input
Output Impedance Matching Input. This input tunes the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin is connected directly to VDDQ, which enables
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation is different from those listed in this datasheet.
TDO
Output
TDO for JTAG
TCK
Input
TCK pin for JTAG
TDI
Input
TDI pin for JTAG
TMS
Input
TMS pin for JTAG
NC
N/A
Not connected to the die. It is tied to any voltage level
NC/36M
N/A
Not connected to the die. It is tied to any voltage level
NC/72M
N/A
Not connected to the die. It is tied to any voltage level
NC/144M
N/A
Not connected to the die. It is tied to any voltage level
NC/288M
N/A
Not connected to the die. It is tied to any voltage level
VREF
Input-
Reference
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, Outputs,
and AC measurement points
VDD
Power Supply Power supply inputs to the core of the device
VSS
Ground
Ground for the device
VDDQ
Power Supply Power supply inputs for the outputs of the device
Pin Definitions (continued)
Pin Name
IO
Pin Description
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