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P4C1298-15CI Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C1298-15CI Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 11 page 1 Document # SRAM135 REV OR Revised April 2007 DESCRIPTION TheP4C1298/Larea262,144-bitultrahighspeedstaticRAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Data Retention with 2.0V Supply Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 15/20/25/35/45 ns (Military) Low Power Single 5V±10% Power Supply Output Enable & Chip Enable control functions FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. The P4C1298 is available in a 28-pin 300 mil DIP or SOJ, as well as a 28-pin 350x500 mil LCC package, providing excellent board level densities. DIP (P5, C5) SOJ (J5) LCC (L5) |
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