CY7C1304DV25
Document #: 38-05628 Rev. *A
Page 2 of 18
Selection Guide
CY7C1304DV25-167
Unit
Maximum Operating Frequency
167
MHz
Maximum Operating Current
400
mA
Pin Configuration
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1304DV25 (512K x 18)
1
2
34
567
89
10
11
A
NC
Gnd/144M
NC/36M
WPS
BWS1
K
NC
RPS
NC/18M
Gnd/72M
NC
B
NC
Q9
D9
A
NC
K
BWS0
ANC
NCQ8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
AAA
TMS
TDI
Pin Definitions
Name
I/O
Description
D[17:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[17:0] to be ignored.
BWS0, BWS1
Input-
Synchronous
Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during
the current portion of the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 512Kb x 18 (4 arrays each of 128Kb x 18).
Therefore, only 17 address inputs are needed to access the entire memory array. These
inputs are ignored when the appropriate port is deselected.
Q[17:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[17:0] are automatically three-stated.
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