CY7C1177V18-300BZXC datasheet(3/27 Pages) CYPRESS

Part #	CY7C1177V18-300BZXC

Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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3 / 27 page

CY7C1166V18

CY7C1177V18

CY7C1168V18

CY7C1170V18

Document Number: 001-06620 Rev. *C

Page 3 of 27

Logic Block Diagram (CY7C1168V18)

Logic Block Diagram (CY7C1170V18)

CLK

A(18:0)

Gen.

K

Control

Logic

Address

Register

Read Data Reg.

R/W

DQ[17:0]

Output

Logic

Reg.

18

36

18

BWS[1:0]

VREF

18

LD

Control

19

Write

Reg

Write

Reg

CQ

R/W

DOFF

QVLD

18

CLK

A(17:0)

Gen.

K

Control

Logic

Address

Register

Read Data Reg.

R/W

DQ[35:0]

Output

Logic

Reg.

36

72

36

BWS[3:0]

VREF

36

LD

Control

18

Write

Reg

Write

Reg

CQ

R/W

DOFF

QVLD

36

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