CY7C1170V18-333BZXI datasheet(10/27 Pages) CYPRESS

Part #	CY7C1170V18-333BZXI

Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 27 page

CY7C1166V18

CY7C1177V18

CY7C1168V18

CY7C1170V18

Document Number: 001-06620 Rev. *C

Page 10 of 27

Write Cycle Descriptions

The write cycle descriptions of CY7C1166V18 and CY7C1168V18 follows. [2, 8]

BWS0/

NWS0

BWS1/

NWS1

K

Comments

L

L–H

–

During the Data portion of a write sequence

:

CY7C1166V18

− both nibbles (D[7:0]) are written into the device,

CY7C1168V18

− both bytes (D[17:0]) are written into the device.

L

–

L-H During the Data portion of a write sequence

:

CY7C1166V18

− both nibbles (D[7:0]) are written into the device,

CY7C1168V18

− both bytes (D[17:0]) are written into the device.

L

H

L–H

–

During the Data portion of a write sequence

:

CY7C1166V18

− only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1168V18

− only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

L

H

–

L–H During the Data portion of a write sequence

:

CY7C1166V18

− only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1168V18

− only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

H

L

L–H

–

During the Data portion of a write sequence

:

CY7C1166V18

− only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1168V18

− only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H

L

–

L–H During the Data portion of a write sequence

:

CY7C1166V18

− only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1168V18

− only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

–

L–H No data is written into the devices during this portion of a write operation.

The write cycle descriptions of CY7C1177V18 follows. [2, 8]

BWS0

KK

Comments

L

L-H

–

During the Data portion of a Write sequence

, the single byte (D[8:0]) is written into the device.

L

–

L-H

During the Data portion of a Write sequence

, the single byte (D[8:0]) is written into the device.

H

L-H

–

No data is written into the device during this portion of a Write operation.

H

–

L-H

No data is written into the device during this portion of a Write operation.

Note

8. Is based on a write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different

portions of a write cycle, as long as the setup and hold requirements are achieved.

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