11 / 16 page
CY7C1218H
Document #: 38-05667 Rev. *B
Page 11 of 16
Write Cycle Timing[17, 18]
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A: D] LOW.
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
BWE,
BW[A :D]
Data Out (Q)
High-Z
ADV
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
t
OEHZ
t
ADVH
t
ADVS
tWEH
tWES
tDH
tDS
GW
tWEH
tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE
UNDEFINED
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
