5

P4C165

Page 5 of 9

Document # SRAM117 Rev OR

Notes:

11. CE

12. OE is LOW for this WRITE cycle to show t

13. If CE

the output remains in a high impedance state.

-20

AC CHARACTERISTICS—WRITE CYCLE

(V

(2)

14. Write Cycle Time is measured from the last valid address to the first

transitioning address.

Sym.

t

WC

t

CW

t

AS

t

WP

t

AH

t

DW

t

DH

Parameter

Write Cycle Time

Chip Enable Time to End of Write

Address Set-up Time

Write Pulse Width

Address Hold Time

Date Hold Time

Data Valid to End of Write

Max

Min

Max

Min

Max

Min

Max

Min

-15

-25

-35

Unit

15

0

12

0

20

0

15

0

25

0

18

0

35

0

20

0

12

12

0

9

15

15

0

11

18

18

0

13

25

25

0

15

ns

ns

ns

ns

ns

ns

ns

ns

t

AW

Address Valid to End of Write

Write Enable to Output in High Z

t

WZ

7

8

10

14

ns

Output Active from End of Write

t

OW

3333

ns

WRITE CYCLE NO. 1 (WE

WE

WE

WE