CY7C1061BV33
Document #: 38-05693 Rev. *B
Page 3 of 9
AC Test Loads and Waveforms[5]
AC Switching Characteristics Over the Operating Range[6]
Parameter
Description
–10
–12
Unit
Min.
Max.
Min.
Max.
Read Cycle
tpower
VCC(typical) to the first access
[7]
11
ms
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
10
12
ns
tOHA
Data Hold from Address Change
3
3
ns
tACE
CE LOW to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
tLZOE
OE LOW to Low-Z
1
1
ns
tHZOE
OE HIGH to High-Z[8]
56
ns
tLZCE
CE LOW to Low-Z[8]
33
ns
tHZCE
CE HIGH to High-Z[8]
56
ns
tPU
CE LOW to Power-Up[9]
00
ns
tPD
CE HIGH to Power-Down[9]
10
12
ns
tDBE
Byte Enable to Data Valid
5
6
ns
tLZBE
Byte Enable to Low-Z
1
1
ns
tHZBE
Byte Disable to High-Z
5
6
ns
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is
started.
8. tHZOE,tHZCE,tHZWE,tHZBE andtLZOE,tLZCE,t\LZWE,tLZBE arespecifiedwithaloadcapacitance of5pF asin(b)ofAC TestLoads.Transition ismeasured ±200 mV fromsteady-state
voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to
initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317
Ω
R2
351
Ω
Rise time > 1V/ns
Fall time: > 1V/ns
(c)
OUTPUT
50
Ω
Z0 = 50Ω
V
TH = 1.5V
30 pF*
* Capacitive Load consists of all com-
ponents of the test environment.
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