CY7C1062AV25
Document #: 38-05333 Rev. *A
Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with
Power Applied............................................. –55
°C to +125°C
Supply Voltage on VCC Relative to GND
[1] .... –0.5V to +3.6V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
2.5V
± 0.2V
Industrial
–40
°C to +85°C
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
–10
Unit
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
VCC = Min., IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[1]
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX = 1/tRC
Com’l/Ind’l
275
mA
ISB1
Automatic CE Power-down
Current—TTL Inputs
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
Com’l/Ind’l
100
mA
ISB2
Automatic CE Power-down
Current —CMOS Inputs
Max. VCC, CE > VCC – 0.2V,
VIN > VCC – 0.2V, or VIN < 0.2V, f = 0
Com’l/Ind’l
50
mA
Capacitance[2]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 2.5V
8
pF
COUT
I/O Capacitance
10
pF
AC Test Loads and Waveforms[3]
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage.
90%
10%
2.3V
GND
90%
10%
ALL INPUT PULSES
2.5V
OUTPUT
5 pF
Including
Jig and
Scope
OUTPUT
(a)
(b)
R1 317
Ω
167
Ω
R2
351
Ω
VENIN EQUIVALENT
THÉ
1.73V
Rise time > 1 V/ns
Fall time:
> 1 V/ns
(c)
OUTPUT
50
Ω
Z0 = 50Ω
V
TH = V
DD/2
30 pF
Including all Components
of Test Equipment
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