PRELIMINARY
8-Mbit (512K x 16) Static RAM
CY7C1051DV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-00063 Rev. *C
Revised March 9, 2007
Features
• High speed
—tAA = 10 ns
• Low active power
—ICC = 110 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 20 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 48-ball FBGA and 44-pin TSOP II
packages
Functional Description[1]
The CY7C1051DV33 is a high-performance CMOS Static
RAM organized as 512K words by 16 bits.
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,
then data from IO pins (IO0–IO7), is written into the location
specified on the address pins (A0–A18). If Byte HIGH Enable
(BHE) is LOW, then data from IO pins (IO8–IO15) is written into
the location specified on the address pins (A0–A18).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on IO0–IO7.
If Byte HIGH Enable (BHE) is LOW, then data from memory
will appear on IO8 to IO15. See the “Truth Table” on page 8 for
a complete description of Read and Write modes.
The
input/output
pins
(IO0–IO15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,
and WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
512K × 16
ARRAY
A0
IO0–IO7
OE
IO8–IO15
CE
WE
BLE
BHE
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