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P4C116-35L32MB Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C116-35L32MB Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 14 page P4C116/P4C116L Page 5 of 14 Document # SRAM110 REV A AC CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show t WZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. t WC Sym. t CW t AW t AS t WP t AH t DW t DH t WZ t OW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write –10 –12 –15 –20 –25 –35 Unit Min Max Min Max Min Max Min Max Min Max Min Max 15 12 12 0 12 0 10 0 0 8 20 15 15 0 15 0 12 0 0 10 25 18 18 0 18 0 15 0 0 15 35 25 25 0 20 0 20 0 0 15 ns ns ns ns ns ns ns ns ns ns TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CE CE CE CE CONTROLLED)(10) 10 8 8 0 8 0 7 0 0 6 12 10 10 0 10 0 8 0 0 7 |
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