11

ICSSSTUBF32866A

Advance Information

1240—07/17/06

2. Device standard (cont'd)

†

CK

D1•D25

RST

tsu

tpd

CK to PPO

th

tsu

th

tpdm , t pdmss

CK to

DCS

CSR

CK

Q1•Q25

PAR_IN

n

n + 1

n + 2

PPO

n + 3

n + 4

QERR †

tPHL or t PLH

CK to QERR

Unknown input

event

H or L

Output signal is dependent on

the prior unknown input event

Data to PPO Latency

Data to QERR Latency

Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;

RST being held high

Figure 10

If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on

the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or

until RST is driven low.