9

ICSSSTUA32S869B

Advance Information

1173—10/28/05

Register Timing

n + 2

n + 1

n

n + 3

n + 4

RESET#

DCS#

CSR#

CLK

CLK#

tsu

tH

tPD

CLK to Q

tSU

tH

tPD

CLK to PPO

tPD

CLK to PTYERR#

tPD

CLK to PTYERR#

D1 - D4

Q1 - Q14

PAR_IN1,

PAR_IN2

PPO1,

PTYERR1#,

PTYERR2#

(1)

(1)

(2)

(2)

(not used)

PPO2

(2)

Note 1: This range doesn't include D1, D4 and D7 and their corresponding outputs