4-Mbit (256K x 16) Static RAM
CY7C1041D
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05472 Rev. *C
Revised March 31, 2006
Features
• Pin-and function-compatible with CY7C1041B
•High speed
—tAA = 10 ns
• Low active power
—ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
—ISB2 = 10 mA
• 2.0 V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 44-Lead (400-Mil) Molded SOJ and
44-Pin TSOP II packages
Functional Description[1]
The CY7C1041D is a high-performance CMOS static RAM
organized as 256K words by 16 bits. Writing to the device is
accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041D is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Note:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
256K x 16
A0
I/O0–I/O7
OE
I/O8–I/O15
CE
WE
BLE
BHE
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
VCC
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A3
A4
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
VSS
I/O6
I/O4
I/O5
I/O7
A16
A15
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A14
A13
A12
A11
A9
A10
NC
Pin Configurations
Top View
SOJ / TSOPII
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