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CY7C1041CV33
Document #: 38-05134 Rev. *H
Page 6 of 12
Write Cycle[9, 10]
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
7
8
10
10
ns
tAW
Address Set-Up to Write End
7
8
10
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
10
ns
tSD
Data Set-Up to Write End
5
6
7
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low-Z[7]
33
3
3
ns
tHZWE
WE LOW to High-Z[7, 8]
56
7
8
ns
tBW
Byte Enable to End of Write
7
8
10
10
ns
Switching Waveforms
Read Cycle No. 1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
AC Switching Characteristics[5] Over the Operating Range (continued)
Parameter
Description
-10
-12
-15
-20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE, BLE
CURRENT
ICC
ISB
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