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STAC9202 Datasheet(PDF) 14 Page - Integrated Device Technology |
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STAC9202 Datasheet(HTML) 14 Page - Integrated Device Technology |
14 / 135 page ![]() STAC9202 2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES 14 STAC9202 V 1.1 102606 IDT CONFIDENTIAL 1. With +30 dB Boost on, 1.00 Vrms with Boost off. 2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. 3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV 4. Amplitude of THD+N, measured with A-weighting filter, over 20 Hz to 20 KHz bandwidth. 5. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 8. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. 2.4. STAC9202 4V Analog Performance Characteristics If you are interested in using the STAC9202 at 4V Analog, please contact IDT for more information. 2.5. STAC9202 3.3V Analog Performance Characteristics If you are interested in using the STAC9202 at 3.3V Analog, please contact IDT for more information. Spurious Tone Rejection - -100 - dB Attenuation, Gain Step Size ANALOG - 1.5 - dB Attenuation, Gain Step Size DIGITAL - 0.75 - dB Input Impedance - 50 - KW Input Capacitance - 15 - pF VREFout - 0.5 X AVdd - V VREF - 0.45X AVdd 0.5 V Interchannel Gain Mismatch ADC - - 0.5 dB Interchannel Gain Mismatch DAC - - - dB Gain Drift - 100 - ppm/ºC DAC Offset Voltage - 5 10 mV Deviation from Linear Phase - 10 1 deg. All Analog Outputs Load Resistance - 10 - K Ω All Analog Outputs Load Capacitance - - 50 pF HEADPHONE_OUT Load Resistance -32 - Ω HEADPHONE_OUT Load Capacitance - 100 - pF Mute Attenuation - - - dB PLL lock time - 96 200 µsec PLL (or HD Audio Bit CLK) 24.576 MHz clock jitter - 100 300 psec Parameter Min Typ Max Unit |