 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
STAC9202 Datasheet(PDF) 32 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
STAC9202 Datasheet(HTML) 32 Page - Integrated Device Technology |
|
|
32 / 135 page 
STAC9202 2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC WITH DUAL DIGITAL MICROPHONE INTERFACES 32 STAC9202 V 1.1 102606 IDT CONFIDENTIAL 5.4.14. AFG GPIODir [1] Mask1 RW 0x0 Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control [0] Mask0 RW 0x0 Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control Table 36. AFG GPIODir Command Verb Format Verb ID Payload Response Get F17 00 See bitfield table Set1 717 See bits [7:0] of bitfield table 0000_0000h Table 37. AFG GPIODir Command Response Format Bit Bitfield Name RW Reset Description [31:4] Rsvd R 0x0 Reserved [3] Control3 RW 0x0 Direction control for GPIO3 0 = GPIO signal is configured as input 1 = GPIO signal is configured as output [2] Control2 RW 0x0 Direction control for GPIO2 0 = GPIO signal is configured as input 1 = GPIO signal is configured as output [1] Control1 RW 0x0 Direction control for GPIO1 0 = GPIO signal is configured as input 1 = GPIO signal is configured as output [0] Control0 RW 0x0 Direction control for GPIO0 0 = GPIO signal is configured as input 1 = GPIO signal is configured as output Table 35. AFG GPIOEn Command Response Format Bit Bitfield Name RW Reset Description |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
