Electronic Components Datasheet Search |
|
IDT5T93GL02 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
IDT5T93GL02 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 14 page INDUSTRIALTEMPERATURERANGE IDT5T93GL02 2.5VLVDS1:2GLITCHLESSCLOCKBUFFERTERABUFFERII 1 JANUARY 2007 IDT5T93GL02 INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II DESCRIPTION: TheIDT5T93GL022.5Vdifferentialclockbufferisauser-selectablediffer- entialinputtotwoLVDSoutputs. ThefanoutfromadifferentialinputtotwoLVDS outputsreducesloadingontheprecedingdriverandprovidesanefficientclock distributionnetwork. TheIDT5T93GL02canactasatranslatorfromadifferential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless change-over from a primary clock source to a secondary clock source up to 450MHz. SelectableinputsarecontrolledbySEL. Duringtheswitchover,the outputwilldisablelowforuptothreeclockcyclesofthepreviously-selectedinput clock. The outputs will remain low for up to three clock cycles of the newly- selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput. AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications. The IDT5T93GL02 outputs can be asynchronously enabled/disabled. Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple power and grounds reduce noise. The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2007 Integrated Device Technology, Inc. DSC 6759/6 FEATURES: • Guaranteed Low Skew < 50ps (max) • Very low duty cycle distortion < 100ps (max) • High speed propagation delay < 2.2ns (max) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface • Selectable differential inputs to two LVDS outputs • Power-down mode • 2.5V VDD • Available in TSSOP package APPLICATIONS: • Clock distribution FUNCTIONAL BLOCK DIAGRAM GL G PD A1 A1 A2 A2 SEL OUTPUT CONTROL OUTPUT CONTROL Q2 Q2 Q1 Q1 1 0 FSEL |
Similar Part No. - IDT5T93GL02 |
|
Similar Description - IDT5T93GL02 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |