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CY7C1021BN-12VXI Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1021BN-12VXI
Description  1-Mbit (64K x 16) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1021BN-12VXI Datasheet(HTML) 1 Page - Cypress Semiconductor

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1-Mbit (64K x 16) Static RAM
CY7C1021BN
CY7C10211BN
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-06494 Rev. *A
Revised September 28, 2006
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
•High speed
—tAA = 10 ns (Commercial)
—tAA = 15 ns (Automotive)
• CMOS for optimum speed/power
• Low active power
— 825 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb free and non Pb free 44-pin TSOP II and
44-pin 400-mil-wide SOJ
Functional Description[1]
The CY7C1021BN/CY7C10211BN is a high-performance
CMOS static RAM organized as 65,536 words by 16 bits. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021BN/CY7C10211BN is available in standard
44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages.
Customers should use part number CY7C10211BN when
ordering parts with 10 ns tAA, and CY7C1021BN when
ordering 12 ns and 15 ns tAA.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com
Logic Block Diagram
64K x 16
RAM Array
I/O1–I/O8
A7
A6
A5
A4
A3
A0
COLUMN DECODER
512 X 2048
DATA IN
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
DRIVERS
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21
23
24
NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
PinConfigurations
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