CY7C1021BNV33
Document #: 001-06433 Rev. **
Page 4 of 10
Switching Characteristics[3] Over the Operating Range
Parameter
Description
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
4
6
7
ns
tLZOE
OE LOW to Low Z
0
0
0
ns
tHZOE
OE HIGH to High Z[4, 5]
5
6
7
ns
tLZCE
CE LOW to Low Z[5]
3
3
3
ns
tHZCE
CE HIGH to High Z[4, 5]
5
6
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
12
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low Z
0
0
0
ns
tHZBE
Byte Disable to High Z
5
6
7
ns
WRITE CYCLE[6]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
8
8
10
ns
tSD
Data Set-Up to Write End
6
6
8
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[5]
3
3
3
ns
tHZWE
WE LOW to High Z[4, 5]
5
6
7
ns
tBW
Byte Enable to End of Write
8
8
9
ns
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
Description
Conditions[7]
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
Com’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
100
µA
tCDR
[8]
Chip Deselect to Data Retention Time
0
ns
tR
[9]
Operation Recovery Time
tRC
ns
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state
voltage.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
7. No input may exceed VCC + 0.5V.
8. Tested initially and after any design or process changes that may affect these parameters.
9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
