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CY7C1020D Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY7C1020D
Description  512K (32K x 16) Static RAM
Download  11 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1020D Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1020D
512K (32K x 16) Static RAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05463 Rev. *E
Revised February 22, 2007
Features
• Pin- and function-compatible with CY7C1020B
• High speed
—tAA = 10 ns
• Low active power
—ICC = 80 mA @ 10ns
• Low CMOS Standby Power
—ISB2 = 3 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description [1]
The CY7C1020D is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.The input and output
pins (IO0 through IO15) are placed in a high-impedance state
when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
•BHE and BLE are disabled (BHE, BLE HIGH)
• When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO0 through IO7), is written into the
location specified on the address pins (A0 through A14). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the
address pins (A0 through A14).
Reading from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins appears on IO0
to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the “Truth Table” on
page 8 for a complete description of read and write modes.
Logic Block Diagram
32K x 16
RAM Array
IO0–IO7
A7
A6
A5
A4
A3
A0
COLUMN DECODER
DATA IN DRIVERS
OE
A2
A1
IO8–IO15
CE
WE
BLE
BHE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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