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CY7C1020D Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY7C1020D
Description  512K (32K x 16) Static RAM
Download  11 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1020D Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C1020D
Document #: 38-05463 Rev. *E
Page 6 of 11
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min
Max
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
3mA
tCDR [4]
Chip Deselect to Data Retention Time
0
ns
tR [13]
Operation Recovery Time
tRC
ns
Data Retention Waveform
Switching Waveforms
Read Cycle No.1 (Address Transition Controlled) [14, 15]
Read Cycle No.2 (OE Controlled) [15, 16]
4.5V
4.5V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
ICC
HIGH
IMPEDANCE
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
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