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P4C147-25PM Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C147-25PM Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 10 page 1 Document # SRAM103 REV A Revised October 2005 P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Low Power Operation – 715 mW Active –10 (Commercial) – 550 mW Active –25 (Commercial) – 110 mW Standby (TTL Input) – 55 mW Standby (CMOS Input) Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 18 Pin 300 mil DIP – 18 Pin CERPACK – 18 Pin LCC (290 x 430 mils) – 18 Pin LCC (295 x 335 mils) DESCRIPTION The P4C147 is a 4,096-bit ultra high speed static RAM organized as 4K x 1. The CMOS memory requires no clocks or refreshing, and have equal access and cycle times. InputsarefullyTTL-compatible. TheRAMoperates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption in both active and standby modes. In addition to very high performance, this device features latch-up protection and single-event-upset protection. The P4C147 is available in 18 pin 300 mil DIP packages, an 18-pin CERPACK package, and 2 different LCC packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P1, D1, C9), CERPACK (F1) SIMILAR LCC (L7, L7-1) |
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