7

1186G—04/16/07

ICSSSTUB32871A

Register Timing

CK

Qn

tsu

CK

n

n + 1

n + 2

n + 3

n + 4

DCSn

RESET

tACT

th

tPDM, tPDMSS

CK to Q

PARIN

tsu

th

tPHL, tPLH

CK to PTYERR

tPHL

CK to PTYERR

PTYERR

H, L, or X

H or L

(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a

minimum time of t

(max) to avoid false error.

ACT

Figure 4

RESET switches from L to H

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