6

COMMERCIALTEMPERATURERANGE

IDT74SSTU32865

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Inputs

Output

RESET

DCS0

DCS1

CLK

CLK

ΣΣΣΣΣ of Inputs = H (D0 - D21)

HL

H

↑↓

Even

L

H

HL

H

↑↓

Odd

L

L

HL

H

↑↓

Even

H

L

HL

H

↑↓

Odd

H

H

HH

L

↑↓

Even

L

H

HH

L

↑↓

Odd

L

L

HH

L

↑↓

Even

H

L

HH

L

↑↓

Odd

H

H

HHH

↑↓

XX

PYTERR

0

(4)

H

X

X

L or H

L or H

X

X

PYTERR

0

(4)

L

XorFloating

XorFloating

XorFloating

XorFloating

XorFloating

XorFloating

H

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

↑ = LOW to HIGH

↓ = HIGH to LOW

2. PARIN arrives one clock cycle after the data to which it applies

3. This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles, or until

RESET is driven LOW.

4. Output level before the indicated steady-state conditions were established.